During the final test of bipolar integrated circuits, or chips, test systems may operate with electrical signals having rise times as fast as 0.4 ns/V. During a wafer level test, multiple outputs of a Device Under Test (DUT) are typically caused to switch simultaneously. This switching generates abrupt changes in the DUT power supply voltage rails, causing the DUT logic gates to erroneously change state. The erroneous change of state results from what is known as a "Delta-I problem". The Delta-I problem occurs because the test system power supply cannot supply the transient switching currents required by the DUT.
Delta-I is considered, for the purposes described herein, to be a change in test system power supply current, both amplitude and slew rate, as a function of a change in a logical state of the DUT.
Power supply decoupling, in the form of capacitors, is a well known technique that is employed to augment the DUT transient power requirements and serves primarily to reduce fluctuations in the voltage applied to the DUT. The overall effectiveness of capacitive decoupling is inversely proportional to the magnitude of the inductance between the decoupling capacitors and the DUT. The larger the magnitude of the inductance, the more pronounced the Delta-I problem becomes because the current through the inductance associated with the power supply lines cannot change instantaneously. The inductance therefore tends to inhibit the required change in current, thus resulting in a transient drop in DUT power supply voltage. As a result, effective DUT power supply capacitive decoupling requires low inductance paths from the power supply and/or decoupling capacitors to the DUT.
It can thus be appreciated that a technique is required for routing power to the DUT such that a significant amount of inductance is not added to the DUT power buses. What is also required is a technique for routing power to a DUT that enables an optimum physical placement of the decoupling capacitors relative to the DUT, while not adversely impacting signal I/0 routing between the DUT and the tester.
In U.S. Pat. No. 4,922,324, May 1, 1990, entitled "Semiconductor Integrated Circuit Device" Sudo discloses decoupling capacitors mounted on metal patterns within a package chip cavity, the metal patterns being connected to sides of the package.
In U.S. Pat. No. 4,879,588, Nov. 7, 1989, entitled "Integrated Circuit Package" Ohtsuka et al. disclose power supply and ground wiring on a periphery of a Multilayer Ceramic (MLC) integrated circuit package.
In U.S. Pat. No. 4,875,087, Oct. 17, 1989, entitled "Integrated Circuit Device Having Strip Line Structure Therein" Miyauchi et al. disclose the use of capacitors in an insulating layer with reduced cross-section conductors to make triplate strip line impedance match a microstrip line impedance.
In U.S. Pat. No. 4,827,327, May 2, 1989, entitled "Integrated Circuit Device Having Stacked Conductive Layers Connecting Circuit Elements Therethrough" Miyauchi et al. disclose high speed connections on a side of package for obtaining a lowered inductance.
In U.S. Pat. No. 4,725,878, Feb. 16, 1988 entitled "Semiconductor Device" Miyauchi et al. disclose GND, power and signal connections on a side of a package. Ground potential lines surround high speed signal lines to form a pseudo-stripline. Impedance is said to be controlled by running the lines on the side of package as opposed to going through internal vias.
In U.S. Pat. No. 4,654,694, Mar. 31, 1987, entitled "Electronic Component Box Supplied with a Capacitor" Val discloses side connections to place a capacitor in close proximity to a chip or, alternatively, to a chip and GND/Power I/0.
In U.S. Pat. No. 4,577,214, Mar. 18, 1986, entitled "Low-Inductance Power/Ground Distribution in a Package for a Semiconductor Chip" Schaper discloses a chip package having a chip cavity and power and ground planes which, together with insulation, form capacitors.
In U.S. Pat. No. 4,288,841, Sept. 8, 1981, entitled "Double Cavity Semiconductor Chip Carrier" Gogal discloses a double chip carrier having power/voltage planes connected to edge castellations.
What is not taught by this prior art, and what is thus one object of the invention to provide, is an improved integrated circuit test structure for routing power to a DVT while not adding a significant amount of inductance and, thus, reducing the effectiveness of power supply decoupling capacitors.
A further object of the invention is to provide an improved integrated circuit test structure that enables an optimum physical and electrical placement of decoupling capacitors, relative to the DUT, for minimizing power conductor inductance and also for minimizing interference with signal I/0 routing between the DUT and a test system.